Plasmonics

(((''&rsquo;Plasmonics is an exploding new field of science and technology in which the flow of light can be modeled at the nanoscale using metallic nanostructures. This newly found ability is rapidly impacting every facet of optics and photonics and is enabling a myriad of exciting technologies&rsquo''; – Professor Mark Brongersma, Stanford University, CLEO 2008)))
==Sub Wavelength Light Confinement==
Plasmonics are a nascent field of research harboring immense potential for optical interconnections and processing at nano-scale. In general, &rsquo;plasmonics&rsquo; stands as a common name for all technologies utilizing the properties of metallic structures at optical frequencies. 
==Nano Interconects==
One of the important challenges for future technology is the implementation of [Computing|optical interconnects on microprocessor chips], solving the problems of signal delay and power consumption. However, it is well known that dielectric waveguides need to have the dimension of the core comparable to the wavelength of light being guided through them. For example, when guiding light in the 1.55 μm window, single mode fiber has a core diameter of approximately 10 μm, InP (indium-phosphide) waveguides are of ~1 μm scale, while Si (silicon) on SiO2 (silicon-dioxide, silica) waveguides are the smallest dielectric waveguides used, with ~0.4 μm size. For dense optical integration on microprocessor chips these dimensions are unacceptably large. As CMOS transistors of today converge to 40 nm size, the optical waveguides become order of magnitude larger then the targeted components. Plasmonic interconnects are intended to bridge this gap in size between CMOS components and optical waveguides. 

This is possible thanks to a unique property of metals at optical frequencies. Sommerfield  was the first to point out that metal surfaces can guide electromagnetic waves, as Maxwell’s equations allow for the self-sustaining solution at the metal-to-dielectric interface. These solutions are, in fact, optical modes, called surface plasmon polaritrons (SPPs). Physically, an SPP is a collective oscillation of the surface charge existing at the interface. Some examples are shown below. 
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| [imageauto|Examples of Plasmonic Modes|{UP}Projects/Plasmonics/image001.jpg]
| [imageauto|Examples of Plasmonic Modes|{UP}Projects/Plasmonics/image002.gif]
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The key ability or property of metal surfaces that makes them interesting for nano scale photonic implementation is the ability to tightly confine the optical mode. Putting two metal plates close together, we construct the gap (or slot) plasmon waveguide. 
Gap waveguides with width as small as 20 nm have been investigated intensively. These waveguides also have high optical loss (~100dB/mm), and can only be used over short distances (~10 μm), which is precisely what they are intended for: short distance interfaces between optical waveguides and electronic components. Recently, ideas to merge the strong sides of plasmonic (tight confinement and sharp bending) and dielectric (low loss) waveguides have been discussed by some authors, opening new horizons in nanophotonics. 
[imageauto|Fig 2. Novel hybrid plasmonic – dielectric waveguide, Lee and Kim, CLEO 2008 &#0091;QTuD6&#0093;|{UP}Projects/Plasmonics/image003.gif]
Other implementations of plasmonics mainly include highly efficient parametric mixers, as the high optical confinement results in high energy density, giving rise to pronounced nonlinear effects. A fair portion of research in nanophotonics is steered towards the properties of metallic nano-shells and arrays of such structures. Due to local breaking of symmetry such arrays can be designed to have new properties or tailor the properties already existing in bulk materials, such as second order nonlinearities, additional plasmon frequencies in the IR region and similar. 
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| [imageauto|Gold nano-particle arrays and their field distribution, Kauranen et. al, CLEO 2008 &#0091;QTuD6&#0093;|{UP}Projects/Plasmonics/image004.gif]
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Our group is interested in pursuing theoretical investigation and simulation of nano scale plasmonic interconnects as well as fabrication and testing. Particularly we wish to investigate the design of low-loss, low crosstalk on-chip plasmonic interconnects and vertical plasmonic interconnect for multi-plane chip design.   
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