Low-latency, scalable, and high-throughput interconnection is essential for future high-performance computing. As massively parallel computing architectures and large data storage systems on the scale of petaFLOPs and petaBytes are being deployed today, the critical performance bottleneck has shifted from the computing systems to the communication infrastructure. All-optical interconnects can benefit from the inherent parallelism and high capacity of Wavelength Division Multiplexing (WDM). We propose an all optical switching architecture that consists of tunable wavelength converters, an AWGR, and a distributed control plane, towards scalable, contention-free optical interconnects for high performance computing networks. The architecture leverages the advantages of WDM's parallelism, using a proactive technique to alleviate contending conditions, to reduce the switching latency, and to enhance the throughput.


1. Current Electrical Switches in Data Center

  • Topology: hierarchies of switches, with expensive, non-commodity switches at the top of the hierarchy
  • Latency: electrical switches have very high latency, especially with multistage topologies
  • Scalability: layered switching networks either require a few special purpose switches (expensive) or many cheap switches, The port density of high-end switches limits overall cluster size.

2. Requirements of switches/networks in high-performance computing

  • Data-Loss sensitive networks: data loss is not allowed
  • Delay-sensitive networks: end-to-end delay should be as low as possible -- need huge bandwidth and fast switching speed
  • Scalable networks: should be able to connect at least thousands of nodes easily with simple topology

AWGR-based Optical Switch

Architecture of Optical Interconnection
Architecture of Optical Interconnection

  • An arrayed waveguide grating router (AWGR) allows multiple inputs to connect to the same output by using different wavelengths enabling the switching fabric to be contention-free
  • The data plane can scale to 2 million x 2 million ports and 42 petabit/second throughput with nano-second switching time
  • Uses electrical control plane to process the header (label) of the packets
  • Scalability of the control plane is essential
    • Scalability of control signal ports
    • Scalability of arbitration algorithm
    • Swtiching delay should not scale up the same ways as the number of ports scale up
  • Contention group = k : localized contention probability, scalable arbitration algorithm
  • Electrical buffer(instead of fiber delay line): arbitrary delay control enables easier flow control

Simulation Assessments of Optical Switch

Simulation Assessments of Optical Switch
Simulation Assessments of Optical Switch

Ethernet switch suffers from saturation at a low traffic load optical switch can accommodate heavy traffic load


A novel AWGR-based optical switching architecture is proposed for data center interconnecting networks. Multiple packets can travel on different wavelengths to the same output port simultaneously, thereby reducing the contention probability at the core switch. A credit-based flow control mechanism is adopted to solve the problem of buffer overflow at the receiver side. Overall, the simulation results show that the proposed switch architecture is advantageous in latency and throughput over Ethernet.